In the prior art, AC coupling capacitors are designed between multiple chips communicating with each other because that: according to PCIE (PCI-Express) standards, a DC bias voltage set at a transmitting end (named as Tx) is V_bias (less than 3.6V), while a DC bias voltage set at a receiving end (named as Rx) is 0V. The difference of the DC bias voltages set at Tx and Rx makes DC common mode voltages of the signals at Tx and Rx different. Further, the different DC common mode voltages of the signals at Tx and Rx mean that the AC coupling capacitors are necessary for blocking DC and delivering AC.
Inserting the AC coupling capacitors between the chips communicating with each other provides many benefits to the physical link design. For example, the compatibility between different systems can be implemented, such as allowing for different chip processes for Tx and Rx, allowing for different system architectures for Tx and Rx and so on, so that different processes/architecture/supply voltages/grounds can be selected by the designers for Tx and Rx in a flexible way. Also, a risk of over-voltage can be avoided. These above benefits are very useful for communication link design across different systems.
However, designing the AC coupling capacitors between the chips communicating with each other also brings many defects. In particular, these AC coupling capacitors take up considerable PCB area and bring cost adding; FIG. 1 shows a 16×PCIE link design example between NVIDIA PCIE bridge chip BR04 and GPU, wherein 64 pieces of AC coupling capacitors are required for 16 lanes between the two chips. In addition, pads and test points of the AC coupling capacitors cause impedance discontinuity which degrades the signal integrity on such high speed (5 Gbps) data exchange link.
In practical applications, designing the AC coupling capacitors between the chips communicating with each other is very useful for cross-platform PCIE link design, like motherboard and graphics card, to make the different voltages of their PCIE signals compatible and avoid the over-voltage. However, for the chips on the same platform (especially on the same PCB board), if they have similar processes/architecture, and can share the same PCIE power supply and the same ground, then they can have the same common mode voltages for PCIE signals. For this case, it does more harm than good to employ the AC coupling capacitors in accordance with the PCIE standards due to the many defects caused by such design.
Therefore, it is required to provide a technical solution to solve the above problems in the conventional communication system between multiple chips.